Consumer electronic products such as televisions, digital cameras, cellular telephones, media content players, etc., help to satisfy consumer demand for basic communications and entertainment services. Data storage components play an important role in the operation of these devices. Data storage devices include RAM, ROM, flash memory products, etc.
An important feature of data storage devices is memory cell density. There are many approaches to increasing the memory cell density of memory arrays. One approach involves reducing the channel length between the source and the drain of transistors associated with memory cells in a memory array. This allows the size of each memory cell to be reduced which in turn facilitates the provision of denser memory arrays. Another approach to increasing memory cell density is embodied in a commercially available flash memory product called MirrorBit™ Technology from Spansion, located in Sunnyvale, Calif.
In flash memory arrays that use MirrorBit technology, the use of MirrorBit memory cells effectively doubles their intrinsic density by storing two physically distinct bits on opposite sides of the memory cells. Each bit that is stored within a cell serves as a binary unit of data (either a logic one or zero) that is mapped directly to the memory array.
An exemplary MirrorBit™ memory device includes a semiconductor substrate with spaced apart source and a drain regions (both typically having N-type conductivity) formed in a substrate. An oxide-nitride-oxide (ONO) layered stack is formed on the top surface of the substrate between the two bit lines. A gate electrode, which typically comprises an N or N+ polysilicon layer, is formed over the ONO stack. The ONO stack includes a first or bottom dielectric layer (often referred to as a bottom tunnel oxide), a charge storing nitride layer, and a second or top dielectric layer of oxide.
Some challenges associated MirrorBit™ devices are related to structural and functional features of the device. For example, it can be difficult to reduce the size or pitch of the cell because the storage element of the above-mentioned flash memory cell can be planar (the oxide, nitride and oxide layers are all horizontal layers formed one on top of the other on the silicon substrate). Moreover, as it regards operations such as the erasure of a Mirrorbit™ cell such as by hot hole injection, because hot holes bombard the interface between the substrate and the bottom tunnel oxide, the interface as well as the bottom tunnel oxide can be damaged causing undesirable interface states and degraded reliability over program/erase cycling.
In order to increase memory density, a FIN structure is desirable in more advanced non-volatile memory technology. However, conventional fabrication methodologies can provide results that can affect the operation of the fabricated MirrorBit™ devices. Problematic features of devices fabricated from conventional methodologies include rough FIN sidewall silicon surfaces, sharp corners and edges in the FIN structure between top surface and sidewalls, non-uniform coverage of the tunnel oxide and early breakdown at the corners and edges due to enhanced electric field.
It should be appreciated that rough sidewall silicon surfaces can result in interface traps. Because of mismatched surface orientations of the silicon FIN sidewalls and the tunnel oxide layer formed over them, interface stresses can result. Importantly, defects can be easily formed at points in the interface where the materials are imperfectly matched. FIG. 1 shows how the formation of the FIN structure can result in damaged sidewall surfaces 101 that include terraces 103 in the sidewalls that are the root cause of high tunnel oxide-silicon interface trap density. Interface traps trap hot electrons that are intended to tunnel through the oxide layer.
In addition, sharp corners and edges of the FIN structure between its top surface and sidewalls can contribute to breakdown at the corners and edges. Referring again to FIG. 1, even though an electric field can be uniformly provided the electric field that results can be concentrated and more intense at the top edges 105 of the FIN structure. As a result, the likelihood of tunnel oxide breakdown at such points is greater. Tunnel oxide breakdown can cause a loss of charge from the charge storage cell structure. As a result, programmed data can be lost.
As can be seen from the above discussion, conventional approaches to fabricating memory cells are inadequate. These approaches can precipitate undesirable consequences that negatively affect device function.